Manufacturer Part #
74LVC138APW,118
74LVC Series 3.6 V 3-to-8 Line Decoder/Demultiplexer Inverting - TSSOP-16
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| Mfr. Name: | Nexperia | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:2500 per Package Style:TSSOP-16 Mounting Method:Surface Mount | ||||||||||
| Date Code: | 1821 | ||||||||||
Product Specification Section
Nexperia 74LVC138APW,118 - Product Specification
Shipping Information:
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ECCN:
EAR99
PCN Information:
N/A
File
Date
Part Status:
Active
Active
Nexperia 74LVC138APW,118 - Technical Attributes
Attributes Table
| Logic Circuit: | Decoder/Demux |
| Family: | A/LVC/E/H/U |
| No of Functions / Channels: | 1 |
| Supply Voltage-Nom: | 2.7|3.6V |
| Package Style: | TSSOP-16 |
| Mounting Method: | Surface Mount |
Features & Applications
The 74LVC138APW,118 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
The 74LVC138A accepts three binary weighted address inputs (A0, A1 and A2) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7). The 74LVC138A features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
Features:
- 5 V tolerant inputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Inputs accept voltages up to 5.5 V
- Demultiplexing capability
- Multiple input enable for easy expansion
- Ideal for memory chip select decoding
- Active LOW mutually exclusive outputs
- Output drive capability 50 Ohm transmission lines at 125 Cel
- Complies with JEDEC standard no. 8-1A
- ESD protection:
- HBM EIA/JESD22-A114-A exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- Specified from -40 to +85 Cel and -40 to +125 Cel
Pricing Section
Global Stock:
220
USA:
220
Product Variant Information section
Available Packaging
Package Qty:
2500 per
Package Style:
TSSOP-16
Mounting Method:
Surface Mount