Nexperia | 74AUP1G86GW,125

Because of the incompatibility of the CD4000 series of chips with the previous TTL family, a new standard emerged which combined the best of the TTL family with the advantages of the CD4000 family. It was known as the 74HC (High performance silicon gate) family of devices.

With HC/HCT logic and LS-TTL logic competing in the market it became clear that a logic device that combined high speed, with low power dissipation and compatibility with older logic families was needed. A whole range of newer families has emerged that use CMOS technology. Some of the more important family designators of these newer devices includes LV/LVT/ALVT.

NXP supports a wide range of speed and performance options, with a focus on reduced power consumption and smaller size.  The advanced CMOS processes deliver robust performance and have driven the expansion of the low-power 1.8- and 3.3-V logic families. All logic families are characterized and specified from -40 to +125 °C.

The 74AUP1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G86 provides the single 2-input EXCLUSIVE-OR function.

The 74AUP1G86GW,125 is a 5V Low Power 2-input Exclusive OR Gate in TSSOP5.