NXP | PCA9516APW,118

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The PCA9516A is a CMOS integrated circuit intended for application in I 2 C and SMBus systems. While retaining all the operating modes and features of the I2 system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9516A enables the system designer to divide the bus into five segments off of a hub where any segment to segment transition sees only one repeater delay. It can also be used to run different buses at 5 V and 3.3 V or 400 kHz and 100 kHz buses where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required.

Two or more PCA9516As cannot be put in series. The PCA9516A design does not allow this configuration. Since there is no direction pin, slightly different "egal low voltage levels are used to avoid lock-up conditions between the input and the output of each repeater in the hub. A "regular LOW" applied at the input of a PCA9516A will be propagated as a "buffered LOW" with a slightly higher value on all the enabled outputs. When this "buffered LOW" is applied to another PCA9515A, PCA9516A, or PCA9518 in series, the second PCA9515A, PCA9516A, or PCA9518 will not recognize it as a "regular LOW" and will not propagate it as a "buffered LOW" again. The PCA9510/9511/9513/9514 and PCA9512 cannot be used in series with the PCA9515A, PCA9516A, or PCA9518 but can be used in series with themselves since they use shifting instead of static offsets to avoid lock-up conditions.

The PCA9516APW-T is a 5-channel I2C hub with a delay time of 75nS. It has a capacitance – input of 6pF, a current – supply of 5mA, and a voltage – supply of 2.3 V ~ 3.6 V. It is 16-pin and is packaged in a TSSOP. The PCA9516APW-T comes in tape and reel format.