Manufacturer Part #
LPC1769FBD100,551
IC MCU 32BIT 256KB FLASH 100LQFP
NXP LPC1769FBD100,551 - Product Specification
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NXP LPC1769FBD100,551 - Technical Attributes
Family Name: | LPC17xx |
Core Processor: | ARM Cortex M3 |
Program Memory Type: | Flash |
Flash Size (Bytes): | 512kB |
RAM Size: | 64kB |
Speed: | 120MHz |
No of I/O Lines: | 70 |
InterfaceType / Connectivity: | CAN/Ethernet/I2C/I2S/SPI/SSP/UART/USB |
Peripherals: | CAN/Ethernet/I2C/I2S/On-Chip-ADC/PWM/SPI/SSP/UART/USB/Watchdog |
Number Of Timers: | 4 |
Supply Voltage: | 2.4V to 3.6V |
Operating Temperature: | -40°C to +85°C |
On-Chip ADC: | 8-chx12-bit |
Watchdog Timers: | 1 |
Package Style: | LQFP-100 |
Mounting Method: | Surface Mount |
Features & Applications
The LPC1769 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
Features:
- ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included
- ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)
- Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 100 MHz operation with zero wait states
- In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software
- On-chip SRAM includes
- Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers
- Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays
- Split APB bus allows high throughput with few stalls between the CPU and DMA
- Serial interfaces
- Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options
- Available as 100-pin LQFP package (14 × 14 × 1.4 mm)
Applications:
- eMetering
- Alarm systems
- Lighting
- White goods
- Industrial networking
- Motor control
Available Packaging
Package Qty:
90 per Tray
Package Style:
LQFP-100
Mounting Method:
Surface Mount