Nexperia | 74LVC74APW,118

The 74LVC74APW is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Features:

• 5 V tolerant inputs for interlacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Complies with JEDEC standard JESD8-B/JESD36
• ESD protection:
  • HBM JESD22-A114D exceeds 2000 V
  • CDM JESD22-C101C exceeds 1000 V
• Specified from -40 Cel to +85 Cel and -40 Cel to 125 Cel