Name: Nexperia 74HC4053PW,118
Brand: Nexperia
SKU: 6827455
Price: 0.11 USD
Availability: InStock

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Image for illustration purposes only,
refer to technical specifications

Manufacturer Part #

74HC4053PW,118

74HC Series 10 V SMT Triple 2-Channel Analog Multiplexer/Demultiplexer -TSSOP-16

74HC4053PW,118 Datasheet 74HC4053PW,118 Documentation User Guide
ECAD Model: Convert this file for your ECAD tool by downloading the free Library Loader. Learn more about ECAD model.
Mfr. Name:	Nexperia
Standard Pkg:	Product Variant Information section Available Packaging Package Qty: 2500 per Reel Package Style: TSSOP-16 Mounting Method: Surface Mount
Date Code:	2502

Nexperia 74HC4053PW,118 - Technical Attributes

Logic Circuit:	Mux/Demux
Family:	A/HC/T/U
No of Functions / Channels:	6
Supply Voltage-Nom:	5V
Supply Current:	16µA
Power Dissipation:	500mW
Propagation Delay:	60ns
Operating Temperature:	-40°C to +125°C
Capacitance:	3.5pF
No of Inputs:	6
No of Outputs:	Triple
No of Pins:	16
Moisture Sensitivity Level:	1
Package Style:	TSSOP-16
Mounting Method:	Surface Mount

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Features & Applications

The 74HC4053PW is a high-speed Si-gate CMOS device and is pin compatiblewith the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.

The 74HC4053 is triple 2-channel analog multiplexer/ demultiplexer with a common enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn).

Features:

Low ON resistance:
- 80 W (typical) at VCC - VEE = 4.5 V
- 70 W (typical) at VCC - VEE = 6.0 V
- 60 W (typical) at VCC - VEE = 9.0 V
Logic level translation:
- To enable 5 V logic to communicate with ±5 V analog signals
Typical ‘break before make’ built in
Complies with JEDEC standard no. 7A
ESD protection:
- HBM EIA/JESD22-A114-C exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Applications:

Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating