Manufacturer Part #
M2GL010-VF256I
IGLOO 2 FPGA, 256 VFPGA 14x14
| | |||||||||||
| | |||||||||||
| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:119 per Tray | ||||||||||
| Date Code: | 2132 | ||||||||||
Microchip M2GL010-VF256I - Product Specification
Shipping Information:
ECCN:
PCN Information:
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the IGLOO� 2 FPGA and SmartFusion� 2 SoC FPGA Datasheet of devices.Description of Change: The following is a summary of the changes in revision B of this document.� Updated Table 3-7 by adding FCS158 related information (FD-292).� Updated the information against Access time with feed-through write timing in Table 3-229 to Table 3-233 (FD-276).
Microchip has released a new Datasheet for the AN4153 Board and Layout Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs of devices.Description of Change: The following is a summary of changes made in this revision: 1. Updated 1.1.2. Power Supply Sequencing. 2. Updated 1.2.2. I/O Glitch During Power-Down.Reason for Change: To Improve Productivity
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx FPGA device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In ProgressEstimated Implementation Date:December 16, 2021 (date code: 2151)
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In Progress
PCN Status: Final notificationPCN Type: Manufacturing ChangeDescription of Change:Release of an update to application note AN4153 (AC393) to include Smartfusion2/IGLOO2 FPGA VDD surge current when exiting system controller suspend mode case for selected products in FPGA family, including M2Sx and M2GLx devices..Impacts to Data Sheet: NoneChange Impact:NoneReason for Change:Release of the updated application note AN4153 section 1.3 �Limiting VDD surge current� which now includes the use case of Smartfusion2/IGLOO2 FPGA VDD surge current when exiting system controller suspend mode.Change Implementation Status:CompleteEstimated Implementation Date:June 23, 2021 (date code: 2126)
Part Status:
Available Packaging
Package Qty:
119 per Tray