onsemi | NB100LVEP91DWG

The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential LVNECL output signals (−2.5 V / −3.3 V).

To accomplish the level translation the LVEP91 requires three power rails. The VCC pins should be connected to the positive power supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 µF capacitors. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low state, and Q outputs to a high state, which will ensure stability.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Key Features:

• Maximum Input Clock Frequency > 2.0 GHz Typical
• Maximum Input Data Rate > 2.0 Gb/s Typical
• 500 ps Typical Propagation Delay
• Operating Range:
• VCC = 2.375 V to 3.8 V
• VEE = −2.375 V to −3.8 V
• GND = 0 V
• Q Output will Default LOW with Inputs Open or at GND
• Pb−Free Packages are Available

Benefits:

• Design Flexibility

Learn more about the NB100LVEP91 Family of Translators