Référence fabricant
M2S090TS-1FGG484I
M2S Series 64 kb RAM 512 kb Flash IGLOO2 & SmartFusion2 SoC FPGA - FPBGA-484
| | |||||||||||
| | |||||||||||
| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :60 par Cut Tape | ||||||||||
| Code de date: | |||||||||||
Microchip M2S090TS-1FGG484I - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Microchip has released a new Errata for the SmartFusion�2 Device Errata of devices. If you are using one of these devices please read the document located at SmartFusion�2 Device Errata.Notification Status: FinalDescription of Change: Added 1.25. Avoid eNVM Page Lock and Unlock if Code is Being Executed from eNVM both in Release and Debug ModeImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 20 Apr 2023NOTE: Please be advised that this is a change to the document only the product has not been changed.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the SmartFusion2 Microcontroller Subsystem User Guide of devices.Notification Status: FinalDescription of Change:� Remapping eNVM data from eNVM_1 memory block to Cortex�-M3 Code space is not permitted for SmartFusion� 2 M2S090/150 and IGLOO� 2 M2GL090/150 devices. For information about eNVM remapping and limitation, see the note under Figure 4-28.� Timing models for Fabric to MSS interrupts have been updated with additional time delay. This changes the timing arcs of nets and interface between Fabric to MSS interrupts. For more information about the updated timing arcs, see PCN 17005A.� Updated 1.5.2.3. Embedded Trace Macrocell to include information about timing arcs update from Fabric to Embedded Trace Macrocell.� Updated 10.5.1. SGMII Interface Configuration to include information about timing arcs update from SerDes to Fabric.� Updated 22.3.1. Configuring the FIIC Using the Libero SoC to include information about timing arcs update from Fabric to MSS interrupts.� The document was converted to Microchip template.� The document number was changed to DS50003495 from UG0331.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 10 Mar 2023
Microchip has released a new Datasheet for the IGLOO� 2 FPGA and SmartFusion� 2 SoC FPGA Datasheet of devices.Description of Change: The following is a summary of the changes in revision B of this document.� Updated Table 3-7 by adding FCS158 related information (FD-292).� Updated the information against Access time with feed-through write timing in Table 3-229 to Table 3-233 (FD-276).
Microchip has released a new Datasheet for the AN4153 Board and Layout Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs of devices.Description of Change: The following is a summary of changes made in this revision: 1. Updated 1.1.2. Power Supply Sequencing. 2. Updated 1.2.2. I/O Glitch During Power-Down.Reason for Change: To Improve Productivity
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx FPGA device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In ProgressEstimated Implementation Date:December 16, 2021 (date code: 2151)
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In Progress
Microchip has released a new Product Documents for the SmartFusion�2 Device Errata of devices.Notification Status: FinalDescription of Change: The following is the summary of changes in revision A:1. The document was updated to Microchip template.2. The document number was changed from 55900196 to DS80000978.3. Updated content in 1.11. Arm� Cortex�-M3 Register Corruption Under Very Specific Literal Loads from eNVM and Cache Miss/Hit Sequences section.Impacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 10 December 2021
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
60 par Cut Tape