
Référence fabricant
M2GL005-TQG144I
IC FPGA 84 I/O 144TQFP
Microchip M2GL005-TQG144I - Spécifications du produit
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Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the IGLOO? 2 FPGA and SmartFusion? 2 SoC FPGA Datasheet of devices.Description of Change: The following is a summary of the changes in revision B of this document.? Updated Table 3-7 by adding FCS158 related information (FD-292).? Updated the information against Access time with feed-through write timing in Table 3-229 to Table 3-233 (FD-276).
Microchip has released a new Datasheet for the AN4153 Board and Layout Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs of devices.Description of Change: The following is a summary of changes made in this revision: 1. Updated 1.1.2. Power Supply Sequencing. 2. Updated 1.2.2. I/O Glitch During Power-Down.Reason for Change: To Improve Productivity
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60 par Tray