Référence fabricant
A3P250-FGG144I
ProASIC3 Series 250000 System Gate 97 I/O 1.575 V Surface Mount FPGA-FPBGA-144
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :160 par Tray | ||||||||||
| Code de date: | 2345 | ||||||||||
Microchip A3P250-FGG144I - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Microchip has released a new Datasheet for the ProASIC�3 Flash Family FPGAs with Optional Soft ARM Support of devices.Notification Status: FinalDescription of Change: In the previous version of the document, there was an error in the migration process to the Microchip template where information related to QN132 devices was not removed. This mistake has been corrected in the current revision. � Corrected misaligned images�Figure 1-1, Figure 1-2, Figure 1-3, and Figure 2-2. � Updated Figure 2-39 as per Revision B of the document.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 May 2023
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Revision History:June 25, 2021: Issued initial notification.February 10, 2022: Issued final Notification under eSign# E000089324. Initial PCN was issued with reference Memo # ML062021004D & TRB# WW22. Attached the qualification report. Provided estimated first ship date to be on February 28, 2022.February 15, 2022: Re-issued the Final notification to correct the affected CPN list.Description of Change:Qualification of ASEM as a new assembly site for selected Microsemi products available in 144L, 256L, and 324L LFBGA, 281L and 288L TFBGA packages.Reason for Change:To improve productivity by qualifying ASEM as a new assembly site.
Revision History:June 25, 2021: Issued initial notification.February 10, 2022: Issued final Notification under eSign# E000089324. Initial PCN was issued with reference Memo # ML062021004D & TRB# WW22. Attached the qualification report. Provided estimated first ship date to be on February 28, 2022.Description of Change:Qualification of ASEM as a new assembly site for selected Microsemi products available in 144L, 256L, and 324L LFBGA, 281L and 288L TFBGA packages. Pre and Post Change Summary: See attachedImpacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by qualifying ASEM as a new assembly site.Note: Because of capacity constraints that have been observed throughout the industry there may be limited or no inventory available as identified in the pre-change.Change Implementation Status:In ProgressEstimated First Ship Date:February 28, 2022 (date code: 2210)Note: Please be advised that after the estimated first ship date customers may receive pre and post change parts.Time Table Summary: See attached
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
160 par Tray