Référence fabricant
M2S005S-VFG400I
ARM® Cortex®-M3 System On Chip (SOC) IC series FPGA - 5K Logic Modules 166MHz 40
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :90 par Tray | ||||||||||
| Code de date: | |||||||||||
Microchip M2S005S-VFG400I - Spécifications du produit
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Informations PCN:
Microchip has released a new Errata for the SmartFusion�2 Device Errata of devices. If you are using one of these devices please read the document located at SmartFusion�2 Device Errata.Notification Status: FinalDescription of Change: Added 1.25. Avoid eNVM Page Lock and Unlock if Code is Being Executed from eNVM both in Release and Debug ModeImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 20 Apr 2023NOTE: Please be advised that this is a change to the document only the product has not been changed.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the IGLOO� 2 FPGA and SmartFusion� 2 SoC FPGA Datasheet of devices.Description of Change: The following is a summary of the changes in revision B of this document.� Updated Table 3-7 by adding FCS158 related information (FD-292).� Updated the information against Access time with feed-through write timing in Table 3-229 to Table 3-233 (FD-276).
Microchip has released a new Datasheet for the AN4153 Board and Layout Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs of devices.Description of Change: The following is a summary of changes made in this revision: 1. Updated 1.1.2. Power Supply Sequencing. 2. Updated 1.2.2. I/O Glitch During Power-Down.Reason for Change: To Improve Productivity
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx FPGA device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In ProgressEstimated Implementation Date:December 16, 2021 (date code: 2151)
PCN Status:Final NotificationPCN Type:Document ChangeDescription of Change:Implement change of memory density from 4GB to 2GB on selected Microsemi M2GLxx, RT4Gxx and 5962-16xx device families available in various packages.Impacts to Data Sheet:NoneChange ImpactNoneReason for Change:To improve productivity by implementing change of memory density from 4GB to 2GB.Change Implementation Status:In Progress
Microchip has released a new Product Documents for the SmartFusion�2 Device Errata of devices.Notification Status: FinalDescription of Change: The following is the summary of changes in revision A:1. The document was updated to Microchip template.2. The document number was changed from 55900196 to DS80000978.3. Updated content in 1.11. Arm� Cortex�-M3 Register Corruption Under Very Specific Literal Loads from eNVM and Cache Miss/Hit Sequences section.Impacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 10 December 2021
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
90 par Tray