Référence fabricant
ATSAMA5D26C-CU
SAMA5D2 Series 3.3 V 500 MHz 32-BIT ARM-Based Microprocessor - LFBGA-289
| | |||||||||||
| | |||||||||||
| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :119 par Tray | ||||||||||
| Code de date: | 2325 | ||||||||||
Microchip ATSAMA5D26C-CU - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Microchip has released a new Errata for the SAMA5D2 Family Silicon Errata and Data Sheet Clarification of devices.Description of Change: Updated 1. Silicon Issue Summary. Added in 6. Controller Area Network (MCAN): - 6.13. Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes Added in 17. Secure Digital MultiMedia Card Controller (SDMMC): - 17.4. SDMMC I/O calibration does not workNOTE: Please be advised that this is a change to the document only the product has not been changed.
Revision History:October 07, 2021: Issued initial notification.August 11, 2022: Issued final notification. Attached the Qualification Report. Provided estimated first ship date to be on August 30, 2022. Revised the post change die attach material for ATK.Description of Change:Qualification of ATK as an additional assembly site for selected ATSAMA5D26 and ATSAMA5D27 device families available in 289L LFBGA (14x14x1.4mm) package.Reason for Change:To improve on-time delivery performance by qualifying ATK as an additional assembly site.
Microchip has released a new Product Documents for the SAMA5D2 Series Silicon Errata and Data Sheet Clarification of devices.Description of Change:1) Updated 1. Silicon Issue Summary.2) Deleted from 6. Controller Area Network (MCAN):- Message order inversion when transmitting from dedicated Tx Buffers configured with same message ID. Reason for Change: To Improve Productivity Date Document Changes Effective: 15 Mar 2022
Microchip has released a new Product Documents for the SAMA5D2 Series Data Sheet of devices.Description of Change:1) Global: Editorial changes throughout.2) System Controller: Updated Block Diagram.3) External Memories: I/O Lines Usage vs. Operating Mode: updated unit.4) CPU System Bus Matrix (CPUMX)a) Block Diagram: added.b) Description: updated.c) Embedded Characteristics: updated.d) Remap: updated.5) 18. Matrix (H64MX/H32MX)a) Table Host to Client Access on H32MX: updated.b) Table Peripheral Identifiers:-updated PMC/PID1, PIT/PID3, WDT/PID4 and RSTC/PID73-updated Note(3)6) Watchdog Timer (WDT)a) Block Diagram: updated.b) Functional Description: updated.c) WDT_CR: updated LOCKMR description.7) Reset Controller (RSTC)a) Block Diagram: modified.b) Embedded Characteristics: updated.c) 32.768 kHz Crystal Oscillator Failure Detection Reset: added.d) Reset State Priorities: updated.e) RSTC_SR: updated RSTTYP description.f) RSTC_MR: added SCKSW at index 1, and description.8) Real-time Clock (RTC)a) Embedded Characteristics: updated.b) Waveform Generation: updated.c) RTC_CALR: updated.d) Updated bit descriptions in RTC_CR, RTC_MR, RTC_TIMALR, RTC_CALALR.9) Slow Clock Controller (SCKC)a) Description: updated.b) Block Diagram: updated.c) Functional Description: updated.10) Clock Generator: 12 MHz RC Oscillator Clock Frequency Adjustment: deleted.11) Power Management Controller (PMC)a) Throughout: SLCK renamed to TD_SLCK.b) Figure Main System Bus Clock Controller: updated.c) Programmable Clock Controller: updated.d) Asynchronous Partial Wake-Up: updated.e) Register Summary: offset 0x0110 now �reserved�.f) Updated:- CKGR_MOR- PMC_IER- PMC_IDR- PMC_SR- PMC_IMR12) Parallel Input/Output Controller (PIO)a) General Purpose or Peripheral Function Selection: updated.b) Open-Drain Mode: added note.c) Input Glitch and Debouncing Filters: updated.13) DDR-SDRAM Controller (MPDDRC)a) Product Dependencies, Initialization Sequence: added new step in initialization sequencesb) MPDDRC_CR: updated DIS_DLL and NDQS descriptions.14) Static Memory Controller (SMC)a) Embedded Characteristics: updated NFC_RAM characteristics.b) HSMC_PMECCFG: updated SPAREEN and AUTO bit descriptions.15) DMA Controller (XDMAC)a) Updated memory-to-memory transfer information in:- XDMAC Transfer Software Operation- XDMAC Software Requirements- XDMAC_CC16) LCD Controller (LCDC)a) Embedded Characteristics: modified bullets on Output mode.b) Window Position, Size, Scaling and Striding Attributes: table title changed to �Window Size� from �YUV Mode and Window Size�.c) YUV Frame Buffer Memory Mapping: replaced �interleaved� with �packed� throughout.17) Gigabit Ethernet MAC (GMAC)a) Embedded Characteristics, Priority Queueing in the DMA: updated.b) 1588 Timestamp Unit: updated.c) Updated table Receive Buffer Descriptor Entry.d) Data Paths with Packet Buffers Included: modified figure (GMII becomes PHY TX Interface, PHY RX Interface) Updated MAC TransmitBlock.e) Interrupts: modified first sentence.f) GMAC_NCR: modified bit descriptions.g) GMAC_NCFGR: modified text for DBW and IRXER.h) GMAC_TSR: added text for TXGO and HRESP.i) GMAC_RBQB, GMAC_TBQB: modified text.j) GMAC_RXUDAR, GMAC_TXUDAR: added.18) USB Device High Speed Port (UDPHS)a) Block Diagram: updated.b) UDPHS_CTRL: updated EN_UDPHS bit description19) USB Host High Speed Port (UHPHS)a) UHPHS_ASYNCLISTADDR: removed sentence referring to non-existing UHPHS_CTRLDSSEGMENT register.b) Corrected reset values for:- UHPHS_HCSPARAMS- UHPHS_HCCPARAMS- UHPHS_PORTSCx20) Flexible Serial Communication Controller (FLEXCOM)a) Figure 46-2 and Figure 46-3: updatedb) RS485 Mode: Updated figure Example of RTS Drive with Timeguard and added Notc) Local Loopback Test Mode: addedd) Data Transfer:- Table SPI Bus Protocol Mode: modified- Figure titles modified to S
Description of Change:Qualification of MPHL as additional final test site for selected ATSAMA5D2xx device family in 289L LFBGA (14x14x1.4mm) package.Reason for Change:To improve manufacturability by qualifying MPHL as additional final test site.Revision History:July 30, 2021: Issued Initial NotificationAugust 23, 2021: Re-issued initial notification to update the Notification Subject, Description of Change, Pre and Post Change Summary and Reason for Change to reflect both ASE9 and MPHL in Post change as final test site.January 27, 2022: Issued Final Notification. Attached the qualification report and updated the timetable summary. Corrected the typo on one of the final test site listed in the revision history of August 23, 2021 from ASCL to ASE9.Estimated First Ship Date:March 2, 2022 (date code: 2210)
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
119 par Tray