Alliance Memory | AS7C34098A-12TCN

Equal address access and cycle times of 10/12/15/20 nano-seconds with output enable access times of 4/5/6/7 nano-seconds are ideal for high-performance applications. The chip enable input  permits easy memory expansion with multiple-bank memory systems.

The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable and chip enable. Data on the input pins I/O1–I/O16 is written on the rising edge of write enable (write cycle 1) or chip enable (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable or write enable. A read cycle is accomplished by asserting output enable and chip enable, with write enable high.

The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. The device is available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.