DSPIC30F4011-30I/PT in Tray by Microchip | Digital Signal Controller (DSC)

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Image for illustration purposes only,
refer to technical specifications

Manufacturer Part #

DSPIC30F4011-30I/PT

dsPIC30F Series 2 kB RAM 48 kB Flash 16-Bit Digital Signal Controller - TQFP-44

DSPIC30F4011-30I/PT Datasheet DSPIC30F4011-30I/PT Documentation Programming Specifications AN1017--Sinusoidal Control of PMSM Motors with dsPIC30F DSC AN1044--Data Encryption Routines for dsPIC® Devices User Guide Errata Reference Manual Quick Start Guide
ECAD Model: Convert this file for your ECAD tool by downloading the free Library Loader. Learn more about ECAD model.
Mfr. Name:	Microchip
Standard Pkg:	Product Variant Information section Available Packaging Tray TraySelected Variant Qty: 1+ / Web Price: $7.01 / Stock: 815 Qty: 1+$7.01 Stock: 815 Package Qty: 160 per Tray Package Style: TQFP-44 Mounting Method: Surface Mount
Date Code:	2412

Microchip DSPIC30F4011-30I/PT - Technical Attributes

Family Name:	dsPIC30F
Core Processor:	dsPIC
Program Memory Type:	Flash
Flash Size (Bytes):	48kB
RAM Size:	2kB
Speed:	40MHz
No of I/O Lines:	30
InterfaceType / Connectivity:	CAN/I2C/SPI/UART
Peripherals:	CAN/I2C/On-Chip-ADC/PWM/SPI/UART/Watchdog
Number Of Timers:	5
Supply Voltage:	2.5V to 5.5V
Operating Temperature:	-40°C to +85°C
On-Chip ADC:	9-chx10-bit
Watchdog Timers:	1
Package Style:	TQFP-44
Mounting Method:	Surface Mount

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Features & Applications

The DSPIC30F4011-30I/PT is a high-performance motor control digital signal controller with an operating voltage range of 2.5 to 5.5 V and a program memory of 48 kB, available in TQFP-44 package.

Features:

High-Performance Modified RISC CPU:
- Modified Harvard architecture.
- C compiler optimized instruction set architecture.
- 84 base instructions with flexible addressing modes.
- 24-bit wide instructions, 16-bit wide data path.
- 16 x 16-bit working register array.
- Up to 30 MIPs operation:
  - DC to 40 MHz external clock input.
  - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x).
- Peripheral and External interrupt sources.
- 8 user selectable priority levels for each interrupt.
- 4 processor exceptions and software traps.
- Primary and Alternate interrupt Vector Tables.
DSP Engine Features:
- Modulo and Bit-Reversed Addressing modes.
- Two, 40-bit wide accumulators with optional saturation logic.
- 17-bit x 17-bit single cycle hardware fractional/ integer multiplier.
- Single cycle Multiply-Accumulate (MAC) operation.
- 40-stage Barrel Shifter.
- Dual data fetch.