Manufacturer Part #
ATSAML11D16A-MU
SAML11: 64KB Flash 16KB SRAM 32MHz ARM Cortex-M23 32-Bit Microcontroller-VQFN24
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:490 per Tray Package Style:VQFN-24 Mounting Method:Surface Mount | ||||||||||
| Date Code: | |||||||||||
Microchip ATSAML11D16A-MU - Product Specification
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Microchip has released a new Product Documents for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices. If you are using one of these devices please read the document located at SAM L10/L11 Family Silicon Errata and Data Sheet Clarification.Notification Status: FinalDescription of Change:1) Updated the device ID in SAM L10 Family Silicon Device Identification.2) The following errata were added in this revision: a) ADC: 2.1.3 SEQSTATE b) NVMCTRL: 2.22.2 Random Hardfaults in WakingImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 Mar 2022NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new Product Documents for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change: The SPI, I2S, and I2C standards use the terminology "Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client" respectively. These terms have been updated throughout this document for this revision.This revision contains numerous typographical updates, and formatting updates.Obsolete Data Sheet Clarifications have been removed in this update.The following errata were added in this revision:� RTC: 2.9.12 Active Layer Protection� SERCOM I2C: 2.10.11 Automatic Acknowledge� TC: 2.13.4 PER register (8-bit mode)� EVSYS: 2.18.3 Spurious Overrun� EVSYS: 2.18.4 Software Event� EVSYS: 2.18.5 PAC Write-Protection� OSCCTRL: 2.19.4 FDPLL96M On Demand in Standby� OSCCTRL: 2.19.5 DFLLULP Dithering ModeNVMCTRL: 2.22.1 Data FLASH Silent Access and ScramblingImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 15 Jul 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
Microchip has released a new Product Documents for the SAM L10/L11 Family Data Sheet of devices.Notification Status: Final Description of Change: The following additions or updates were done during this revision:1. General1.1 Throughout the entire document all references of �Master� were changed to �Host,� and �Slave� was changed to �Client,� where applicable1.2 Previous Revision histories were consolidated to clean up the flow of the document2. Features - Added new information for PWM Modes using TC peripherals.3. Analog Peripherals Consideration - Updated the note for Caution, and the Analog Signal Components Interconnections Diagram4. Memories4.1 Updated Flash with a new Caution note4.2 Updated Data Flash with a new Caution note5. SAM L11 Specific Security Features - Added two new figures to SAM L11 Memory Mapping Configuration Summary:5.1 SAM L11 Default Memories Mapping - 64KB Flash Case5.2 SAM L11 Default Memories Mapping - 16/32KB Flash Case6. Clock System - Updated the figure in On Demand Clock Requests to read CHEN instead of CLKEN7. MCLK7.1 Updated Clock Ready Flag with text regarding the CPUDIV value7.2 Updated the INTFLAG Register with new text for the CKRDY bitfield8. FREQM8.1 Updated the Block Diagram. CLK_REF is now CLK_REF_MUX8.2 Updated CLK_REF to read CLK_REF_MUX in Principle of Operation8.3 Updated CLK_REF to read CLK_REF_MUX in Measurement9. PM9.1 Added all new text and a new caution note to SRAM Power Switch Configuration9.2 Added a caution note to the PWCFG Register, and updated the existing KB Flash tables and added new tables for 32KB and 16KB9.3 Corrected a typographical error in the INTFLAG Register10. OSCCTRL10.1 An important note was added to External Multipurpose Crystal Oscillator (XOSC) Operation10.2 An important note was added to Clock Failure Detection Operation10.3 Replaced text in the last paragraph of Initialization, Enabling, Disabling, and Resetting10.4 Updated the XOSCCTRL Register with new text and note for the STARTUP Bitfield11. OSC32KCTRL11.1 Updated Overview with new text11.2 Updated 32KHz External Crystal Oscillator (XOSC32K) Operation with a new important note11.3 Added new text and an important note to Clock Failure Detection Operation11.4 Updated bitfield descriptions in the following registers with new important notes, and new text:11.4.1 RTCCTRL11.4.2 XOSC32K12. RTC - Updated the following registers with new notes:12.1 COUNT (COUNT32)12.2 COUNT (COUNT16)13. DMAC - Updated the following registers with new bit alignment values:13.1 BASEADDR13.2 WRBADDR13.3 DESCADDR14. PORT - Updated the figure in the Functional Description15. EVSYS - Updated Sleep Mode Operation with a new note and a new row to the Event Channel Sleep Behavior Table16. SERCOM - Updated I/O Lines with new text17. SERCOM USART17.1 Updated I/O Lines with new text17.2 Updated the bit description for the MAXITER bit in the CTRLC Registe18. SERCOM SPI 18.1 Updated I/O Lines with new text18.2 Updated the DOPO bitfield with new text in the CTRLA Register19. SERCOM I2C19.1 Updated I/O Lines with new text19.2 Updated the CTRLB Register with new bitfield access values for the CMD and QCEN bitfields20. TC20.1 Updated Capture Operations with new notes20.2 Updated Event Capture Action to read Event Capture Action on Events or I/Os, added new text and corrected capitalization in the diagram20.3 Updated Period and Pulse-Width (PPW) Capture Action to read Period and Pulse-Width (PPW/PWP) Capture Action on Events, and updated capitalization in the diagram20.4 Updated Pulse Width Capture Action to read Pulse-Width (PW) Capture Action on Events, and updated the capitalization in the diagram20.5 Updated Time Stamp Capture to read Time-Stamp Capture on Events or I/Os and removed the term Capture from the diagram20.6 Removed non-applicable text from Events20.7 Added new notes to the following registers:2
PCN Status: Final notificationPCN Type: Manufacturing ChangeDescription of Change:Qualification of MMT as an additional assembly site for selected Atmel ATSAML10D1xA, ATSAML11D1xA, ATSAMD11D14A, ATSAMD10D1xA, ATSAMD09D14A and ATMPS001D14A device families available in 24L VQFN (4x4x0.9mm) package.Impacts to Data Sheet: Yes. Package Outline Drawing (POD)Change Impact:NoneReason for Change:To improve on-time delivery performance by qualifying MMT as an additional assembly site.Change Implementation Status:In ProgressEstimated First Ship Date:May 28, 2021 (date code: 2122)
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Microchip ATSAML11D16A-MU - Technical Attributes
| Family Name: | SAML11 |
| Core Processor: | ARM Cortex M23 |
| Program Memory Type: | Flash |
| Flash Size (Bytes): | 64kB |
| RAM Size: | 16kB |
| Speed: | 32MHz |
| No of I/O Lines: | 17 |
| InterfaceType / Connectivity: | I2C/LIN/SPI/USART |
| Peripherals: | DMA/POR/PWM/Watchdog |
| Supply Voltage: | 1.62V to 3.63V |
| Operating Temperature: | -40°C to +85°C |
| On-Chip ADC: | 5-chx12-bit |
| Watchdog Timers: | 1 |
| Package Style: | VQFN-24 |
| Mounting Method: | Surface Mount |
Features & Applications
Available Packaging
Package Qty:
490 per Tray
Package Style:
VQFN-24
Mounting Method:
Surface Mount
