Référence fabricant
74AHC74D,118
74AHC Series 5.5V D-Type Flip-Flop Set/Reset Positive-Edge Trigger - SOIC-14
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| Nom du fabricant: | Nexperia | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :2500 par Reel Style d'emballage :SOIC-14 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | 2339 | ||||||||||
Product Specification Section
Nexperia 74AHC74D,118 - Spécifications du produit
Informations de livraison:
L'article ne peut être envoyé à certains pays. Voir la liste
L'article ne peut pas être envoyé aux pays suivants:
ECCN:
EAR99
Informations PCN:
N/A
Fichier
Date
Statut du produit:
Actif
Actif
Nexperia 74AHC74D,118 - Caractéristiques techniques
Attributes Table
| Logic Circuit: | D-Type, Flip Flop IC |
| Family: | A/HC/T/U |
| No of Functions / Channels: | 2 |
| Output Characteristics: | Complementary |
| Supply Voltage-Nom: | 2V to 5.5V |
| Power Dissipation: | 0.5W |
| Propagation Delay: | 5.2ns |
| Operating Temperature: | -40°C to +125°C |
| Capacitance: | 3pF |
| No of Inputs: | 2 |
| No of Outputs: | Dual |
| High Level Output Current: | -8mA |
| Low Level Output Current: | 8mA |
| No of Pins: | 14 |
| Quiescent Current: | 2µA |
| Moisture Sensitivity Level: | 1 |
| Style d'emballage : | SOIC-14 |
| Méthode de montage : | Surface Mount |
Fonctionnalités et applications
The 74AHC74D is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74D is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Features and benefits:
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- Input levels:
- For 74AHC30: CMOS level
- For 74AHCT30: TTL level
- ESD protection:
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101C exceeds 1000 V
- Multiple package options
- Specified from -40 Cel to +85 Cel and from -40 Cel to +125 Cel
Pricing Section
Stock global :
10 000
États-Unis:
10 000
Sur commande :
0
Délai d'usine :
8 Semaines
Quantité
Prix unitaire
2 500
$0.0699
7 500
$0.0681
10 000
$0.0676
25 000
$0.0662
37 500+
$0.0648
Product Variant Information section
Emballages disponibles
Qté d'emballage(s) :
2500 par Reel
Style d'emballage :
SOIC-14
Méthode de montage :
Surface Mount