Manufacturer Part #
A3P250-PQG208
ProASIC3 Series 250000 System Gate 151 I/O 1.575 V Surface Mount FPGA - PQFP-208
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:24 per Tray Package Style:PQFP-208 Mounting Method:Surface Mount | ||||||||||
| Date Code: | 2335 | ||||||||||
Microchip A3P250-PQG208 - Product Specification
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Microchip has released a new Datasheet for the ProASIC�3 Flash Family FPGAs with Optional Soft ARM Support of devices.Notification Status: FinalDescription of Change: In the previous version of the document, there was an error in the migration process to the Microchip template where information related to QN132 devices was not removed. This mistake has been corrected in the current revision. � Corrected misaligned images�Figure 1-1, Figure 1-2, Figure 1-3, and Figure 2-2. � Updated Figure 2-39 as per Revision B of the document.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 May 2023
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
Microchip A3P250-PQG208 - Technical Attributes
| System Gates: | 250000 |
| No of I/O Lines: | 151 |
| Operating Frequency-Max: | 350MHz |
| Flash Size (Bits): | 1kb |
| RAM Size (Bits): | 36kb |
| Supply Voltage: | 1.425V to 1.575V |
| Operating Temp Range: | 0°C to 85°C |
| Storage Temperature Range: | -65°C to +150°C |
| Interface Type: | Jtag |
| Temperature Grade: | Commercial |
| Moisture Sensitivity Level: | 3 |
| Package Style: | PQFP-208 |
| Mounting Method: | Surface Mount |
Available Packaging
Package Qty:
24 per Tray
Package Style:
PQFP-208
Mounting Method:
Surface Mount