Nexperia | 74LVT573PW,118

The 74LVT573PW,118 is a 3.3 V octal D-type transparent latch with 3-state output buffer.

This device is controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.

Features:

• Inputs and outputs arranged for easy interfacing to microprocessors
• 3-state outputs for bus interfacing
• Common output enable control
• TTL input and output switching levels
• Input and output interface capability to systems at 5 V supply
• Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
• Live insertion and extraction permitted
• No bus current loading when output is tied to 5 V bus
• Power-up reset
• Power-up 3-state
• Latch-up protection
  • JESD78 class II exceeds 500 mA
• ESD protection:
  • HBM JESD22-A114E exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
• Specified from 40 C to +85 C