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By Nexperia
Switches and multiplexers are widely used to lower total system cost: they enable the designer to base a design on a cheaper microcontroller with a low pin count while still satisfying the application’s requirement for I/O channels. They may also be used to provide signal paths for multiple external sensors, and to implement voltage-level translation.
Nexperia offers a wide range of switches and multiplexers which is listed in the company’s online product selection guide. The purpose of this article is to provide a guide to the basics of switches and multiplexers. There is an important distinction between digital and analog multiplexers: while digital devices can be used for General-Purpose I/O (GPIO) expansion only, analog multiplexers can be used for both GPIO and ADC functions. This article is focused on analog I/O expansion.
The range of switch topologies
CMOS is by far the most widely used IC fabrication process for multiplexers and switches. It offers low cost, high performance, and characteristics which are helpful in common applications. Other processes are used for special applications which require very high bandwidth, but which cost more and consume more power.
To make the connection between the input and output of a switch, multiple configurations are possible.
Three are worthy of note, as shown in Figure 1:
Fig. 1: Topologies of the three common switch configurations
The NMOS pass switch is the simplest and cheapest implementation. It offers low on-resistance when handling small signals. But while this is a simple solution, there are some drawbacks. The most important disadvantage is that the gate-source voltage of the transistor depends on the load, and therefore will not be stable across all load conditions. This results in a load-dependent on-resistance.
Another disadvantage is that the output voltage will not be able to swing to the full supply voltage value.
To an extent, these problems can be overcome by using a charge pump to drive the NMOS gate. This helps to maintain a steady gate-source voltage; but the on-resistance will still increase as the input voltage rises.
The PMOS pass transistor configuration is rarely used. PMOS transistors have higher on-resistance, so they need a larger die area, making them more expensive and subject to higher parasitic capacitance.
The most attractive configuration is the CMOS switch which consists of an NMOS transistor in parallel with a PMOS transistor. The transistors are driven in opposite directions, so both will conduct when the select voltage is High. The result is in the paralleling of the on-resistances of both transistors, and so flat on-resistance across the input-voltage range.
Effect on ADC settling time
Most ADCs have an internal sampling capacitor which is used to store the sampled charge before digitization. Thanks to a combination of input resistance and parasitic capacitances, a settling time will be needed before the measured voltage equals the input voltage.
This settling time can be calculated with Formula 1:
For example, assume that an 8-channel multiplexer is used with this 16-bit ADC to switch a source which has an impedance of 500Ω.
Looking at the datasheet, the typical peak on-resistance for an HEF4051B analog multiplexer at a supply voltage of 5V is 350Ω. Assuming an ADC capacitor of 20pF, the settling time needed for this system would be 11.8 x (500+350) x 20, or 0.2µs.
The functionally compatible 74HCT4851 in the same configuration has peak on-resistance of 59Ω. The result is a shorter settling time of 11.8 x (500+59) x 20, or 0.13µs. So by selecting a different multiplexer, the designer can achieve a 65% reduction in settling time. This is why it is valuable to understand the basic parameters of switches.
Important switch parameters
The table shows the key parameters that should be considered when selecting a switch or multiplexer.
The first parameter to consider is the voltage range. Besides the operating voltage, the amplitude of the signal should be considered. Does the input signal swing to the supply rail, or is only a limited voltage range needed? What are the levels of the select control signal?
The second parameter is the on-resistance of the switch: this value is usually not stable across the full operating range of the product. The value depends on the switch topology, input voltage and operating voltage of the switch.
Figure 2 shows the on-resistance behavior of the various topologies as a function of input voltage.
The on-resistance of a single PMOS switch is plotted in red. This on-resistance value falls when the input voltage increases. Green shows the on-resistance behavior of an NMOS switch. Here, on-resistance increases with an increasing input voltage. When paralleling the PMOS and NMOS switch, the blue plot of on-resistance is obtained. This behavior is commonly shown in the product datasheet.
Fig. 2: On-resistance behavior of various switch topologies
Figure 3 shows a snapshot of on-resistance as a function of the input-voltage range of a 74LVC2G3157 switch. The on-resistance value is dependent on the input voltage as well as the supply voltage.
Fig. 3: On-resistance behavior of the 74LVC2G3157 switch
Peak on-resistance is the highest resistance value at a specified supply voltage. So in Figure 3, peak on-resistance is 34Ω at a supply voltage of 1.8V. Switches also have an inherent temperature dependency, and on-resistance rises when the temperature rises.
Flatness of on-resistance is the difference between the maximum and minimum values at an identical supply voltage and temperature. It is therefore dependent only on the input voltage.
Parasitic capacitances also play an important role in switch selection.
The input capacitance and the parasitic capacitance of the switch in the On or Off state are specified in the datasheet. Together with the load resistor, these form a low-pass filter. The roll-off of the circuit may be calculated or simulated when these values are known. These capacitances also add up to the switch capacitor of the ADC, and therefore influence the settling time.
Bandwidth and Total Harmonic Distortion (THD) are both the consequence of imperfections in the switch. THD is mainly the result of the linearity of on-resistance, and bandwidth is determined by the parasitic capacitances.
Crosstalk is an important parameter when connecting multiple sources to the input of a switch. This parameter determines the residual signal of an unused channel in the output channel. A higher value in dBm means better isolation, and therefore less distortion of the selected signal.
Charge injection is the result of the parasitic capacitances between the gate and drain of the switching elements.
Fig. 4: Gate-drain capacitance affects the output signal
When the select signal goes from High to Low or vice versa, the gate-drain capacitance is charged or discharged and shown in Figure 4. This can be seen in the output signal as a spike or step change. The value, measured in pC, influences an ADC’s sampling time, since the measured value needs to be stable before conversion.
When sampling a signal, leakage current must be considered as well. This parameter causes a gain error in DC measurements.
Fig. 5: Leakage current path in a switch
The leakage current flows through RL//(RS+RON) and is therefore important at higher load resistances, shown in Figure 5. It is possible to compensate for this DC offset through calibration.
Conclusion
Optimizing performance always involves the balancing of trade-offs. An ideal electronic switch does not exist. Bearing in mind the parameters described above will enable the designer to avoid the potential pitfalls.
As a guide to product selection:
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