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Renesas has introduced a microprocessor option for developers who want to base new designs on the RISC-V instruction set architecture.
The Renesas RZ/Five Group of MPUs provides a RISC-V implementation backed by a rich set of memory and communications interfaces. The RZ/Five RISC-V CPU core is an AX45MP Single running at a clock frequency of up to 1 GHz. The MPU also provides a 16-bit interface to high-speed DDR3L or DDR4-1600 DRAM.
For high-speed data transfers, the RZ/Five MPU features a one- or two-channel Gigabit Ethernet interface. It also provides two-channel CAN-FD and USB 2.0 interfaces. Renesas supports comprehensive security protection for connected devices based on the RZ/Five. These include secure boot capability, a cryptography engine, true random number generator, and a 1 kbit one-time programmable memory for key storage.
The RZ/Five is supplied in two versions:
Designers using the RZ/Five can reduce system cost by implementing designs on a four-layer PCB. The 13 mm x 13 mm version is pin-compatible with the RZ/G2UL Arm® Cortex®-A55-based MPU, part number R9A07G043U11GBG#BC0.
Part Number: RTK9743F01S01000BE
The RZ/Five evaluation kit consists of a SMARC v2.1 system-on-module (SOM) board and a carrier board.
The carrier board can be used with the RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SOMs which are compatible with the SMARC v2.1 standard, as well as with the RZ/Five SOM. This means that it provides a flexible platform for evaluating the entire RZ family of devices.
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