Microchip – MCP16501 Cost and Size Optimized PMIC for eMPU
The MCP16501 is a cost and size optimized integrated PMIC, compatible with the latest Microchip’s Microprocessor Units (MPU) and associated DRAM Memories. The SAMA5, SAM9X60 and SAMA7G54 series MPUs are supported by dedicated PMIC variants programmed for the different supply voltages and power sequencing requirements.
The Microchip MCP16501 integrates three DC-DC Buck regulators and one auxiliary LDO, and provides a comprehensive interface to the MPU. All Buck channels can support loads up to 1A and are 100% duty cycle- capable. The 300 mA LDO is provided such that sensitive analog loads can be supported.
The MCP16501’s DDR memory voltage (Buck2 output) is selectable by means of a 3-state input pin. This method allows greater precision in the output voltage setting by eliminating inaccuracies due to external feedback resistors, while minimizing external component count.
The MCP16501 voltage selection set allows easy migration across different generations of memory. The default power channel sequencing is built-in and configured to the requirements of the MPU. The MCP16501 PMIC also features a dedicated pin (LPM) that facilitates the transition to Low-Power modes and the implementation of Backup mode with DDR in self-refresh (Hibernate mode).
The Microchip MCP16501 features a low no-load operational quiescent current and it draws less than 10 μA in full shutdown. Active discharge resistors are provided on each output. All Buck channels support safe start-up into pre-biased outputs.
The MCP16501 is available in a 24-pin 4 mm x 4 mm VQFN package with an operating junction temperature range from -40°C to +125°C.
Parametrics
| Name | Value |
| Vout Max (V) | 3.7 |
| Freq (Hz) | 2000 |
| Duty Cycle Max | 100 |
| Temp Range | Tj = -40 to +125C |
| LDO | 1 Auxiliary |
| LOWQ Mode | Yes |
| Type | PMIC |
| Iq Operating | < 250uA |
| Iq Off (µA) | < 10uA |
| VIN Max (V) | 5.5 |
| VIN Min (V) | 2.7 |
Key Features
- Input Voltage: 2.7V to 5.5V
- Three 1A Output Current Buck Channels with 100% Maximum Duty Cycle Capability
- 2 MHz Buck Channels PWM Operation
- ±1% Voltage Accuracy for DDR (Buck2 Output) and Core (Buck3 Output)
- Low Noise, Forced PWM (FPWM) and Low IQ, Light Load, High-Efficiency Mode Available
- One Auxiliary 300 mA Low-Dropout Linear Regulator (LDO)
- Pin-Selectable Output Voltages for DDR Supply
- Built-in Channel Sequencing, Safe Start-up and Reset Assertion Delay
- Support of Hibernate and Low-Power modes
- Leakage-Free Interfacing to MPU in any Operating Condition through Optimized ESD Protection
- 250 μA Low-Power Mode Typical Quiescent Current (Bucks and LDO ON, No Load)
- 10 μA Maximum Shutdown Current
- Cost and Size-Optimized BOM
- Thermal Shutdown and Current Limit Protection
- 24-Pin 4 mm × 4 mm QFN Package
- -40°C to +125°C Junction Temperature Range
Markets
| Applications
|
